1. Field of the Invention
The present invention relates to an integrated circuit layout having a first circuit connection, a second circuit connection, and MOS transistors, whereby the MOS transistors each have a source connection and a drain connection and a predefined maximum reverse voltage between the source connection and the drain connection, and whereby a maximum value of a voltage swing, achieved between the first circuit connection and the second circuit connection, is greater than a predefined maximum reverse voltage. A source connection of an n-th MOS transistor is connected to a drain connection of an (n−1)-th MOS transistor, whereby the circuit layout changes the potentials at the gate terminals of the (n−1)-th MOS transistor and of the n-th MOS transistor substantially synchronously to a control signal.
2. Description of the Background Art
An integrated circuit layout is known from DE 197 55 134 C1 and DE 199 26 109 A1.
MOS transistors are active components, in which variable space charges form. Examples of such components are semiconductor components such as diodes and transistors.
Two advantages can be achieved simultaneously by the series connection of MOS elements. A first advantage is that market segments that require higher reverse voltages, at least in parts, can be served with a single manufacturing process, optimized for a specific reverse voltage. A second advantage results from the fact that the on-resistance R_on of a MOS transistor in general depends quadratically on its reverse voltage. The dependence on the reverse voltage is even more pronounced for the space requirement to achieve a predefined R_on. Lateral MOS components, depending on the desired reverse voltage, are manufactured using different construction principles. For low-blocking logic components, they are made with a drift zone or magnetoresistor and are designated as MOS. For the medium voltage range around 25 V, MOS without a magnetoresistor but with a drift distance are used (MVMOS, MV=medium voltage), and in the voltage range above about 40 V, so-called HVMOS (HV=high voltage) with drift distance and a magnetoresistor are used. The three construction principles have different constants R_on/square of the reverse voltage. The same applies to the space requirement as a function of the reverse voltage. To achieve the same R_on, as a specific HVMOS has, a series connection of, for example, three MVMOS requires, in one respect, a total of 9 times the gate length of a single MVMOS. The width, however, is less than in HVMOS, so that space can be saved in large output drivers.
Further, circuit layouts are known per se, which have passive components with a reactance disposed between active components. Reference is made to WO 02/23716 as an example of this type of known circuit layout. This publication describes a power amplifier with a series connection of a P-MOS transistor (P-MOS=P-Channel Metal Oxide Semiconductor), an inductor, and an N-MOS transistor (N=N-channel). The two complementary MOS transistors are controlled by input signals that are inverses of one another, each conducting or blocking simultaneously. A load is connected to a tap between one of the two MOS transistors and the inductor of the series connection via an LC network of additional inductors and capacitors. This layout is intended to limit voltage peaks, to which the transistors, as connecting elements of the amplifier, are subjected to values below the breakdown voltages of the transistor. High-frequency applications are cited as typical fields of application.
There is the problem in many technical applications that voltages that exceed the breakdown voltages of conventional semiconductor components are to be controlled statically at the circuit output. For such circuits, special semiconductor components have also been used thus far whose breakdown voltage was increased by additional out-diffused and low-doped space-charge regions.
In series connections of MOS transistors with a voltage across the series connection that is greater than the breakdown voltage of a single MOS transistor, there is the problem that the conductivity of the MOS transistors must be controlled synchronously. In a non-synchronous control in which a first MOS transistor enters a low-resistance state before a second MOS transistor, voltage peaks can occur across the second MOS transistor that exceed its breakdown voltage.